Title :
The chip design of a 32-b logarithmic number system
Author :
Huang, Sheng-Chieh ; Chen, Liang-Gee ; Chen, Thou-Ho
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
30 May-2 Jun 1994
Abstract :
To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log 2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor
Keywords :
arithmetic; digital arithmetic; integrated circuit design; iterative methods; microprocessor chips; 32 bit; IDLA; LNS arithmetic; digit-partition; iterative difference by linear approximation; logarithmic number system; Approximation algorithms; Arithmetic; Chip scale packaging; Costs; Councils; Degradation; Linear approximation; Partitioning algorithms; Programmable logic arrays; Read only memory;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409224
