Title :
On the reduction of reorder buffer size for discrete Fourier transform processor design
Author :
Shen, Wen-Zen ; Tao, Yi-Hsin ; Dung, Lan-Rong
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
30 May-2 Jun 1994
Abstract :
Double RAM buffer technique is widely used in row-column method to decompose the multidimensional transformation. In this paper, we propose a new approach, named single RAM technique. Base on the accurate arrangement of the location and timing of the input and output data, only a single RAM is used as the reorder buffer. Therefore, approximately half of the memory size is reduced. In addition, a long length DFT processor which can handle 1008-point real-valued DFT with nonstop input sequence is presented to demonstrate the benefits of the single RAM buffer technique. Goertzel Algorithm and CORDIC technique are adopted to realize a two level pipeline linear array for attaining higher speed. Besides, based on the symmetric property of real value DFT, we can compute N-point real-valued DFT with a length-N/2 complex-valued DFT
Keywords :
VLSI; buffer storage; digital arithmetic; digital signal processing chips; discrete Fourier transforms; pipeline processing; random-access storage; CORDIC technique; Goertzel algorithm; VLSI; discrete Fourier transform processor design; long length DFT processor; nonstop input sequence; real value DFT; reorder buffer size; single RAM technique; symmetric property; two level pipeline linear array; Computer architecture; Costs; Design engineering; Discrete Fourier transforms; Multidimensional systems; Pipelines; Process design; Random access memory; Read-write memory; Timing;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409225
