Title :
Systolic implementation of counterpropagation networks
Author :
Kwan, Hon-Keung ; Tsand, P.-C.
Author_Institution :
Dept. of Electr. Eng., Windsor Univ., Ont., Canada
Abstract :
A novel implementation of the counterpropagation network with both the recalling and the learning algorithms is presented. The implementation is based on a word-level systolic architecture which consists of two types of basic cells. The final architecture is characterized by regular interconnections, which is very suitable for VLSI implementation
Keywords :
VLSI; learning systems; parallel algorithms; systolic arrays; VLSI implementation; counterpropagation networks; learning algorithms; parallel processing; recalling algorithm; regular interconnections; word-level systolic architecture; Network topology; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on
Conference_Location :
Albuquerque, NM
DOI :
10.1109/ICASSP.1990.116020
