Session 29: Modeling and simulation variability modeling and technology optimization

This session presents novel approaches to modeling variability and technology optimization. The session begins with an invited paper by Christie et al., on rapid design flows for advanced technology path-finding. A rigorous approach to the dynamic large-scale stability of semiconductor circuits and devices is the subject of the second paper by Cappelluti et al., A proposal for breaking through the 60mV/dec. Subthreshold swing limit using ferroelectric materials is presented by Salahuddin and Datta. The role of high-k spacers in sub-20nm FinFETs is discussed next in a paper by Sachid et al., The rest of the session discusses variability issues and their impact on device design. The need to limit layout restrictions is presented by H. Onodera. H. Dadgour et al., will then address grain orientation effects in emerging Metal-Gate Devices. A study of Metal-Gate FinFET variability is presented next by O´uchi et al., This session concludes with a presentation on transport-based dopant mapping in advanced FinFets by Lansbergen et al.