Improving the testability of VLSI circuits through partitioning

The field of test engineering for very large scale integrated (VLSI) circuits is inundated with requirements to improve test coverage, reduce overhead and decrease development time. In response to this is a design methodology that will eliminate the test generation effort. This will reduce overall production costs, and provide a savings for products manufactured in low volumes. The approach utilizes known methods of partitioning circuits into smaller portions. Each portion being fully testable, the entire circuit is fully testable, neglecting portions of the Built-In-Self-Test (BIST) circuit itself. Overall, the results show that for small volume production, this methodology could be the best available option for a large class of circuits. Furthermore, it also provides a high degree of reliability in terms of the quality of the manufacturing test, and does not require expensive test devices, such as high-speed wafer-probe testers. The new design cycle that is presented eliminates time for test generation in lieu of approximately fifteen-percent impact in performance and size