Title :
A fast array architecture for block matching algorithm
Author :
Baek, Jongseob ; Nam, Seunghyun ; Lee, MoonKey ; Oh, Chuldong ; Hwang, Ksoo
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
30 May-2 Jun 1994
Abstract :
The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. Based on two dimensional systolic array, VLSI architecture for an implementation of full-search block matching algorithm is described. The proposed architecture has the following advantages: (1) it allows serial data inputs to save pin counts but performs parallel processing. (2) It is flexible in adaptation to the dimensional change of search window with simple control logic. (3) It has no idle time during the operation. (4) It can operate in real time for videoconference application and EDTV application. (5) It is modular and regular in design, and thus suitable for VLSI implementation
Keywords :
VLSI; digital signal processing chips; image coding; image matching; image sequences; motion estimation; systolic arrays; EDTV; VLSI architecture; block matching algorithm; control logic; image sequence; motion estimation; motion-compensated coding; parallel processing; real time operation; search window; serial data inputs; two dimensional systolic array; videoconferencing; Image coding; Image sequences; Logic design; Motion estimation; Parallel processing; Shift registers; Strontium; Switches; Systolic arrays; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409234
