Title :
VLSI architectures for hierarchical block matching
Author :
Gupta, Gagan ; Chakrabarti, Chaitali
Author_Institution :
Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ, USA
fDate :
30 May-2 Jun 1994
Abstract :
Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area, to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures
Keywords :
VLSI; digital signal processing chips; image matching; image processing equipment; motion estimation; parallel architectures; processor scheduling; real-time systems; scheduling; DSP chips; VLSI architectures; hierarchical block matching; memory organization; memory-efficient architecture; motion estimation technique; onchip memory; scheduling; special-purpose architectures; Bandwidth; Computer architecture; Computer science; Memory architecture; Motion estimation; Process design; Processor scheduling; Very large scale integration; Visual communication;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409235