A high performance FPGA with hierarchical interconnection structure

To overcome the low speed and low density problems in the FPGAs, we must reduce the number of switches used in the routing paths without sacrificing the routability for an FPGA. A hierarchical interconnection architecture for field programmable gate array (FPGA) is described. In every level of the hierarchy, logic blocks or cluster of logic blocks are connected together with switch blocks. Experiments on benchmark circuits are shown. It can be seen that significant improvement on performance is achieved