Title :
A 2½-dimensional systolic array architecture
Author_Institution :
Sch. of Comput. & Math. Sci., Oxford Brookes Univ.
fDate :
30 May-2 Jun 1994
Abstract :
This paper presents a novel 2½-dimensional systolic array architecture. The novel systolic array has a logical three-dimensional communication network, but it can be realized on a two-dimensional wafer surface by making use of multiple-layer metalization or multiple chip module technology. The architectural details are discussed in terms of graph theory. Based on several case study, the computational efficiency and hardware overheads for the proposed array are summarised with respect to conventional systolic arrays
Keywords :
graph theory; matrix multiplication; systolic arrays; 2.5 dimensional systolic array architecture; MCM; computational efficiency; graph theory; hardware overheads; logical three-dimensional communication network; multiple chip modules; multiple-layer metalization; two-dimensional wafer surface; Communication networks; Computational efficiency; Computer architecture; Distributed computing; Electronic mail; Graph theory; Hardware; Signal processing algorithms; Systolic arrays; Topology;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409242
