Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption

Configurable cache tuning architectures for embedded systems applications can dramatically reduce energy consumption. Existing state-of-the-art heuristics to efficiently explore large configurable cache design space has aimed at finding the cache configuration that yields the minimal energy consumption. However, as energy-driven cache optimizations may reach great energy reduction, the overall system performance is often penalized by considering only a single-metric energy cost function. In this paper, we propose an automated exploration mechanism for adjusting two-level cache hierarchies in order to reduce energy consumption for embedded applications, by keeping up the high performance computing. In our experiments, we applied our heuristic to 12 different benchmarks from the MiBench. The results show an average reduction of about 41% in the energy consumption for instruction caches when compared to existing heuristics and a reduction by about 25% the number of cycles needed to execute a given application