Title :
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
Author :
Kuo, J.B. ; Su, K.W. ; Lou, J.H.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
30 May-2 Jun 1994
Abstract :
This paper presents a BiCMOS dynamic multiplier, which is free from race and charge sharing problems, using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit. Based on a 1 μm BICMOS technology, a 1.5 V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; adders; carry logic; multiplying circuits; 1 micron; 1.5 V; 8×8 multiplier; BiCMOS dynamic multiplier; Wallace tree reduction architecture; carry look-ahead; full adder; full-swing BiCMOS dynamic logic circuit; multiplier speed; Adders; BiCMOS integrated circuits; Buildings; CMOS logic circuits; CMOS technology; Clocks; Logic circuits; Logic devices; Logic gates; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409262
