Current input TSPC latch for high speed, complex switching trees

This paper discusses new techniques for obtaining high clock rates with complex n-blocks in True-Single-Phase dynamic latch structures. In this paper we present new dynamic current steering latch structures, and apply them to both CMOS and BiCMOS technologies. In the latter case, we exploit the superior properties of the available bipolar devices to achieve substantial speed increases. The latching technique allows complex n-FET blocks (fan-in between 10 and 20) to be used with the TSPC latch at high data rates (over 150 MHz for a 1.2 μ CMOS process). The n-FET block is built as a minimized binary tree, which we have termed a switching tree, and interpreted as a general look-up table for use in a variety of bit-level systolic array processors