Session 33: Memory technology - DRAM and NOR

This session presents recent advances in 1T DRAM, standard DRAM and NOR flash memory. The 1st Paper by Ki-Whan Song et al., from Samsung demonstrates aggressively scaled 55 nm capacitor-less 1T DRAM cell transistor with non-overlap source and drain. The next paper by T. Ohsawa et al., from Toshiba Corporation proposes autonomous refresh of floating body cell for 1Gb 32nm FBRAM. Hyun Jun Bae at al., from Samsung explore the evaluation of 1T RAM using various operation methods with SOONO device and show the longest retention time ever reported for 1T RAM. T. Schloesser et al., from Qimonda present a 46nm 6F² buried word line DRAM enabling the smallest cell size of 0.013μm² published to date. The invited paper by S.Q. Gu et al., from Qualcomm reviews stackable memory of 3D chip integration for mobile application which provides unique opportunity for high BW and low power. The next paper by Wen-Jer Tsai et al., from Macronix reports on highly punchthrough-immune operation for ultra-short-channel hot-carrier injection type non-volatile memory. Finally, C. Gerardi et al., from STMicroelectronics and CEA-LETI demonstrate excellent performance and reliability of Si nano-crystal 4Mb NOR flash in 90nm.