Session 34: Memory technology - nanoscale poly-FG and charge trap flash non-volatile memories

This session will discuss papers related to nanoscale poly floating-gate and charge trap non-volatile memories. The first two papers are on poly-floating gate technologies, the next three are on charge-trap flash memories and the last two are on 3-D NAND flash memories. In the first paper, Toshiba Corporation reports a floating-gate multi-level NAND flash memory technology scalable to 30nm and beyond technology nodes. In the second paper, Qimonda and the Technical University of Munich present a stochastic model of the program operation in scaled NAND flash memories for investigating the interactions between the memory cell and the memory system. Charge-Trap Flash: The next paper by Numonyx and Politecnico di Milano investigates the Random Telegraph Noise scaling trend for both NAND and NOR flash memories. The fourth paper by Toshiba Corporation presents the scalability of a bulk planar SONOS flash memory with double-tunnel junctions down to 10nm gate length. The next paper by National Tsing Hua and Chiao-Tung University reports a new charge-trap engineered non-volatile memory device with very good memory window and high-temperature data retention. 3-D SONOS Flash: In the fifth paper, Schiltron Corporation presents a novel 3-D stackable high-density flash technology, which combines the smallest TFTs to date in series with strings up to 64 cells in a unique architecture to effectively remove pass disturbs. The last paper by Toshiba Corporation, demonstrates a four NAND string 3-D bit cost scalable flash memory with improved program, erase and disturb operation.