Title :
Sub-50nm DG-TFT-SONOS - the ideal Flash memory for monolithic 3-D integration
Author :
Walker, Andrew J.
Author_Institution :
Schiltron Corp., Mountain View, CA
Abstract :
A revolutionary 3-D stackable sub-50nm double-gate TFT SONOS technology is presented here with series strings of up to 64 cells consisting of the smallest silicon-based TFT´s to date. Read- and program-pass disturbs have been extinguished. Excellent endurance and retention are shown. Monolithic 3-D integration and scalability are ensured through close to zero source/drain diffusion. Finally, comparisons with TANOS are given.
Keywords :
MOS memory circuits; flash memories; thin film transistors; DG-TFT-SONOS; ideal flash memory; monolithic 3-D integration; program-pass disturbs; read-pass disturb; scalability; source-drain diffusion; Dielectric devices; Flash memory; MOSFETs; Nonvolatile memory; Photonic band gap; SONOS devices; Scalability; Technological innovation; Thin film transistors; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796830
