Session 35: CMOS devices and technology - alternative MOSFET device architectures and materials

In this session are reported recent progress in novel CMOS device architecture. The first two papers contain outstanding results obtained on FINFETs technology. Enhancements of SRAM circuit performance are experimentally reported using an independent double gate FINFET device by AIST (Japan). The second paper, by IMEC (Belgium) describes the application of a striking Full Field Extreme UV lithography to the realization of a 0.186 μm² FinFET based SRAM cell. Promising Nanowire transistors results are then reported in the two following works. MIT presents detailed mobility measurements in Gate All Around Uniaxial strained silicon nanowires, featuring a 3.35 nm radius. Moreover, a successful integration of FUSI metal gate has been achieved in undoped silicon nanowires (diameter 7 nm), in a joint effort of both the Institute of Microelectronics and the National University of Singapore. Finally, the last two papers discuss the possible replacement of silicon by germanium as channel material. A record gate length of 60 nm pMOS device was successfully realized by IMEC, underlying the critical role of the silicon passivation layer. Drastic improvements in the interface quality of Germanium substrate with various orientations are reported by the University of Tokyo in the last paper of this section.