Title :
Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φm and VT tune-ability
Author :
Jiang, Y. ; Liow, T.Y. ; Singh, N. ; Tan, L.H. ; Lo, G.Q. ; Chan, D.S.H. ; Kwong, D.L.
Author_Institution :
Inst. of Microelectron., Agency for Sci., Technol. & Res., Singapore
Abstract :
A simple and cost-effective single metal gate scheme was successfully demonstrated to form gate-all-around (GAA) nanowire FETs with optimized dual VT for low power CMOS applications. FUSI gate-induced stress effects were shown to be of great relevance to device performance. At an IOff of 20 pA/mum, superior IOn of 1180 and 405 muA/mum were obtained for NFETs and PFETs at a VDD of 1.2 V.
Keywords :
CMOS integrated circuits; field effect transistors; nanowires; FUSI gate-induced stress effects; gate-all-around single metal FUSI gates; low power CMOS; nanowire FET; voltage 1.2 V; Annealing; Boron; CMOS technology; Doping; FETs; Microelectronics; Silicidation; Silicides; Silicon; Stress;
Conference_Titel :
Electron Devices Meeting, 2008. IEDM 2008. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2377-4
Electronic_ISBN :
8164-2284
DOI :
10.1109/IEDM.2008.4796836
