Performance and functional test of flip-flops using ring oscillator structure

In this work the performance and functional evaluation of D-type flip-flops, considering the presence of asynchronous set and reset signals, is proposed through the use of ring oscillator structure (ROS). Ring oscillators are efficiently applied for combinational gate delay measurements. However, such test strategy cannot be directly applied to sequential cells since the output signal transition is not controlled by a single input signal. Novel ROS stages built using flip-flop are presented. Besides the speed verification, power consumption and aging effect analysis can also be performed over the circuit under test. The proposed test solution is also suitable for a fair comparison of performance between different topologies of flip-flops. This test approach has been validated at the gate level, through functional simulations (VHDL), and at the transistor level, through electrical simulations (SPICE).