Author :
Mitard, J. ; De Jaeger, B. ; Leys, F.E. ; Hellings, G. ; Martens, K. ; Eneman, G. ; Brunco, D.P. ; Loo, R. ; Lin, J.C. ; Shamiryan, D. ; Vandeweyer, T. ; Winderickx, G. ; Vrancken, E. ; Yu, C.H. ; De Meyer, K. ; Caymax, M. ; Pantisano, L. ; Meuris, M. ; H
Abstract :
We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.
Keywords :
MOSFET; germanium; ion implantation; passivation; silicon; EOT scalability; Ge; Si; epi-silicon passivation process; equivalent oxide thickness; gate stack engineering; halo implants; low-temperature passivation scheme; pMOSFET; series resistance; size 65 nm; Fabrication; Implants; MOSFET circuits; Passivation; Photonic band gap; Reproducibility of results; Scalability; Temperature distribution; Thickness control; Tin;
