Layout-aware high performance interconnects for Network-on-Chip design in deep nanometer technologies

As IC geometries continue to shrink into the deep nanometer regime, interconnects can have a large impact on overall system performance, power consumption, cost and reliability. In 90 nm or lower technologies, wiring capacitance dominates gate capacitance, thus rapidly leading to increased interconnect-induced delay. Moreover, coupling capacitance becomes significant between adjacent wires due to tighter geometries and can no longer be ignored as a second order effect. As a consequence, traditional top-down approach taken in design methodology for a NoC based complex SoC designs is no longer effective. This paper address the impact of nanometer layout on the design of NoC, and shows the necessity to consider interconnect parasitic effects in early stages of design even when no physical layout is available. Global interconnects with and without repeater insertion are considered. The effects of the width and spacing of global interconnects on NoC performance such as delay, bandwidth, total repeater area and power dissipation is analyzed.