A 6-bit 50 MHz current-subtracting two step flash converter

Author

Cable, Andrew ; Harjani, Ramesh

Author_Institution

Minnesota Univ., Minneapolis, MN, USA

Volume

5

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

465

Abstract

The design of it 6-bit 50 MHz CMOS-current-subtracting two-step flash A/D converter in 1.2 μm CMOS technology is described. The two-step current-subtracting technique reduces the number of current comparators and their resolution requirements thus reducing both area and power. A new design for a high speed current subtracter is presented. A differential positive feedback technique is used in the current comparators to increase speed while maintaining high resolution. The complete A/D converter, including encoding logic, operates at 50 MHz and dissipates a maximum of 25 mW

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit feedback; current comparators; 1.2 micron; 25 mW; 50 MHz; 6 bit; A/D converter; CMOS technology; current comparators; current-subtracting two step flash converter; differential positive feedback technique; encoding logic; flash ADC; high speed current subtracter; resolution requirements; Analog-digital conversion; CMOS analog integrated circuits; CMOS logic circuits; CMOS technology; Encoding; Feedback; Power dissipation; Quantization; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409411

Filename

409411