Session 37: Process Technology - advanced source-drain engineering and memory processing

This session contains six papers featuring leading edge source/drain engineering and memory processing. The first four papers describe advanced source/drain engineering and the following two papers, including one invited paper, are dealing with innovative memory processing. The first paper from NEC achieves near-scaling-limit bulk CMOS using raised source/drain extensions and millisecond annealing junction. The second paper from Samsung shows the reduction of threshold voltage variability and standby leakage using advanced co-implantation and laser anneal for low power applications. The third paper from Ultimate Junction Technologies, Inc. and Matsushita Electronic Industrial Co. uses self-regulatory plasma doping (SRPD) process to provide conformal doping for FinFET and precise controllable ultra-shallow doping for planar FET. The fourth paper from Toshiba describes thorough material and process evaluation and analyses at atomic level on Pt-incorporated NiSi. The fifth paper is an invited paper from Samsung which presents charge trap flash technology as the promising scaling drive for NAND flash beyond 40nm, with transition from the current floating gate NAND flash memory. The final paper from IMEC reports on the process optimization and characterization of the low temp ALD SrTiO3 on TiN MIM capacitor with record low leakage EOT for DRAM application.