Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM

In the present investigation, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduced power consumption. The eDRAM is usually designed to sustain the worst operating conditions, and the chip is very rarely operated under these conditions. We, thus exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicated that the power consumption can be saved more than 10 times when the chip is normally operated, which is highly significant in the chip operation. This keeps the chip cool and operating temperature will be well under control which helps in averting device degradation and ultimate breakdown.