Reconfigurable K-best MIMO detector architecture and FPGA implementation

Author

Shariat-Yazdi, Ramin ; Kwasniewski, Tad

Author_Institution

Carleton Univ., Ottawa

fYear

2007

fDate

Nov. 28 2007-Dec. 1 2007

Firstpage

349

Lastpage

352

Abstract

In a MIMO communication system, K-best decoding algorithm achieves near optimal performance with reduced complexity. Simulation results show that a reconfigurable MIMO detector can improve system performance over a wide range of operating conditions. In this paper we present a low complexity reconfigurable architecture for implementation of K-best algorithm. Implementation results using FPGA technology demonstrate a throughput of 240 Mbps.

Keywords

MIMO communication; field programmable gate arrays; maximum likelihood decoding; maximum likelihood detection; reconfigurable architectures; FPGA implementation; K-best decoding algorithm; low complexity reconfigurable k-best MIMO detector architecture; maximum-likelihood detector; Bit error rate; Detectors; Field programmable gate arrays; MIMO; Maximum likelihood decoding; Quality of service; Receivers; Signal processing algorithms; System performance; Throughput; FPGA; K-best; MIMO; Reconfigurable hardware;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. International Symposium on

Conference_Location

Xiamen

Print_ISBN

978-1-4244-1447-5

Electronic_ISBN

978-1-4244-1447-5

Type

conf

DOI

10.1109/ISPACS.2007.4445895

Filename

4445895

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2933091