DocumentCode :
2933127
Title :
An architecture of accelerating real-time multimedia for networking applications
Author :
Hsiao, Yi-Mao ; Wang, Chao-Yuan ; Huang, Kuo-Chang ; Chu, Yuan-Sun
Author_Institution :
Nat. Chung Cheng Univ., Chiayi
fYear :
2007
fDate :
Nov. 28 2007-Dec. 1 2007
Firstpage :
357
Lastpage :
360
Abstract :
With the increasing of multimedia application, the network traffic have become heavy and increased the CPU loading. The main limitations for real-time multimedia networking are memory copies and interrupts. In this paper, a proposed system which have a dual CPU architecture will accelerate real-time multimedia transfer on the networking. An FPGA prototyping - Versatile is designed and implemented that has an ARM (hard core) and an Uni-RISC. Compared with the traditional single CPU system, the proposed dual CPU architecture shows 37.89% performing improvement on an FPGA prototyping.
Keywords :
field programmable gate arrays; local area networks; multimedia communication; real-time systems; telecommunication traffic; ARM; Ethernet; FPGA prototyping; Uni-RISC; Versatile; accelerating multimedia; dual CPU architecture; multimedia networking; multimedia transfer; network traffic; networking applications; real-time multimedia; Acceleration; Field programmable gate arrays; Intelligent networks; Kernel; Multimedia systems; Prototypes; Real time systems; Resource management; Signal processing; Telecommunication traffic; Architecture; Dual CPU; FPGA; Multimedia; Network;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. International Symposium on
Conference_Location :
Xiamen
Print_ISBN :
978-1-4244-1447-5
Electronic_ISBN :
978-1-4244-1447-5
Type :
conf
DOI :
10.1109/ISPACS.2007.4445897
Filename :
4445897
Link To Document :
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