A high speed programmable digital FIR filter

Author

Evans, Joseph ; Lim, Y. ; Liu, Bede

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

fYear

1990

fDate

3-6 Apr 1990

Firstpage

969

Abstract

The implementation of a high-speed, programmable finite impulse response (FIR) filter using coefficients consisting of two power-of-two terms is presented. The area and speed performance figures for this application-specific IC (ASIC) demonstrate the superiority of this architecture for high-speed and high-density implementation. This implementation was developed using a relatively primitive CMOS process. Simple λ-rule scaling suggests that by using a 1.25-μm and double-level metal process of the same die size, this architecture will allow the implementation of a filter of approximately 200 taps operating at a 10-MHz sampling rate

Keywords

CMOS integrated circuits; application specific integrated circuits; digital filters; λ-rule scaling; 1.25 micron; 10 MHz; ASIC; CMOS process; application-specific IC; digital FIR filter; double-level metal process; finite impulse response; high speed; Adders; Application specific integrated circuits; CMOS process; Digital filters; Digital signal processing chips; Filtering algorithms; Finite impulse response filter; High speed integrated circuits; Sampling methods; Shift registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.116030

Filename

116030