A 1-Mb STT-MRAM with zero-array standby power and 1.5-ns quick wake-up by 8-b fine-grained power gating

The power gating is one of the key technologies that reduce the operation power of STT-RAMs for enjoying their non-volatility. Especially, the number of memory cells whose supply voltages are simultaneously controlled in the power gating (grain size) is required to be as small as the bit-width in read and write for minimizing the operation power. For this ultra-fine-grained power gating scheme, we proposed a small power line (PL) driver that utilizes an NFET bootstrap circuit. It is found that the size of the macro using this PL driver is almost independent of the grain size with its write and read performance kept constant. Therefore, this PL driver combined with a small grain is shown to realize a nonvolatile embedded memory macro of fast read/write cycles, ultra-low operation power and zero array standby power with no leak path in the PL drivers.