Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability

Increasing the accuracy of circuit delay estimation using Non Linear Delay Model (NLDM) in nanometer range CMOS technologies is highly challenging. To solve this issue, people have started using effective current source model (ECSM) and composite current source model (CCSM), which can both be derived from each other. For a standard cell, ECSM stores certain predefined threshold crossing points (TCPs) of the output voltage waveform with respect to several input transition time (T_R) and load capacitance (C_l) values. In this work, we propose an analytical timing model relating all TCPs with Cl and TR values for inverter standard cell. We derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (T_R, C_l) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum error of 2.5%. We use this model and the derived relationships with cell size to reduce the number of simulations in ECSM library characterization. Due to process, voltage and on-chip temperature (PVT) variation, re-characterization is done at several PVT corners. In addition, layout dependent effects also lead to an unexpected variation in cell performance. To reduce the characterization effort, we derive relationships of variation of our model coefficients and regions of validity with cell size in mechanical stress enabled CMOS technologies, considering cell layout parameters. We also derive relationships of our model´s coefficients with on-chip supply voltage and temperature variations. We use these relationships in reducing number of HSPICE simulations in ECSM re-characterization significantly.