DocumentCode :
2934094
Title :
Real-time H.264 encoder implementation on a low-power digital signal processor
Author :
Yang, Ming-Jiang ; Tham, Jo-Yew ; Rahardja, Susanto ; Wu, Da-Jun
Author_Institution :
Inst. for Infocomm Res., A*STAR, Singapore, Singapore
fYear :
2009
fDate :
June 28 2009-July 3 2009
Firstpage :
1150
Lastpage :
1153
Abstract :
This paper presents a real-time H.264/AVC baseline profile video encoder. The encoder hardware is implemented using a cost-effective, low-power ADI Blackin-561 DSP and related peripherals for real-time video capturing, coding and streaming. The encoder software is developed using a two-stage pipelining framework for efficient parallel video data encoding. A synchronization mechanism with shared memory semaphores is used to schedule the hardware processes and software procedures to acquire the real-time encoding performance. Techniques for reducing the execution time in both stages are also described in this paper. Performance evaluation results verified that the encoder is capable of performing real-time encoding of CIF-resolution and medium-motion VGA-resolution videos, while maintaining good video quality.
Keywords :
video coding; CIF-resolution; H.264 encoder; digital signal processor; embedded media processing; encoder software; medium-motion VGA-resolution videos; shared memory semaphores; video data encoding; video encoder; Automatic voltage control; Digital signal processing; Digital signal processors; Encoding; Hardware; Performance evaluation; Pipeline processing; Software performance; Streaming media; Video sharing; H.264; embedded media processing; multicore DSP; real-time encoder; scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia and Expo, 2009. ICME 2009. IEEE International Conference on
Conference_Location :
New York, NY
ISSN :
1945-7871
Print_ISBN :
978-1-4244-4290-4
Electronic_ISBN :
1945-7871
Type :
conf
DOI :
10.1109/ICME.2009.5202703
Filename :
5202703
Link To Document :
بازگشت