Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design

An analysis of 3D VRRAM is presented, taking into account read/write margin, leakage and power consumption. The results give guidelines for array dimensioning (number of layers / in plane array size) and bias conditions. The read margin is more sensitive to the number of layers than the in plane array size in the matrix, while a tradeoff is found between read margin and total leakage/power. Optimized write bias conditions are determined, which improve both write margin and power consumption as compared to the results using the standard bias schemes. A comparison shows that VRRAM is more promising than stacked 3D RRAM, not only from a cost perspective, but also provides better electrical behavior, both for read and write.