Flip chip package design optimization

Flip chip BGA packaging which was once restricted to high performance systems, where the norm is to customize a package design for a particular application, is now emerging in the ASIC industry as well. Here the need is to be able to provide a high performance low cost package family that will serve a range of low volume and/or cost sensitive applications and the challenge is to have a package design methodology that can be executed early in the package development cycle. Flip chip package design with these constraints is a new field, where conventional ASIC package design methodology cannot be used. Areas that have been traditionally ignored in a wire bond package design need to be addressed in terms of their impact on package cost and performance. The design methodology that is developed and described here, involves a detailed estimation of electrical performance of flip chip packages before package layout. This is performed concurrently with package routing studies to evaluate various design options, allowing the electrical optimization of packages early in the design cycle. As an example of this design process, the development of a family of 5 metal layer organic flip chip packages is described