Abstract :
This paper introduces a verification development platform for RFID reader. The RFID reader is compatible with EPC Class-1, Generation-2 Standard, operating at the 915 MHz band. The UHF RFID reader includes RF analog front end (AFE), the base band and clock. The RFID RF AFE contains transmitting circuit, receiving circuit, frequency synthesize, circulator, etc. The base band contains the FPGA chip, DDR SDRAM, FLASH, A/D, D/A, etc. the FPGA chip is inserted NiosII soft core. This architecture is an advantage for implementing various kinds of RFID standards, and efficiently reduces the design and development time and cost. The platform achieves rapid, flexible and efficient verification and development by changing the soft of NiosII core in FPGA.
Keywords :
DRAM chips; field programmable gate arrays; radiofrequency identification; DDR SDRAM; EPC Class-1; FLASH; FPGA chip; Generation-2 Standard; NiosII core; UHF RFID reader; analog front end; bandwidth 915 MHz; circulator; frequency synthesize; receiving circuit; transmitting circuit; verification development; Circuit synthesis; Clocks; Field programmable gate arrays; Filtering; Filters; Frequency synthesizers; Radio frequency; Radiofrequency identification; Receiving antennas; Standards development; AFE; RFID; baseband;
