Board-level thermal modeling of PBGA and CSP in natural and forced convection

An efficient and fairly accurate methodology for predicting the thermal performance of plastic ball grid array (PBGA) and chip-scale (CSP) packages using computational fluid dynamics (CFD) software is described. Four types of PBGAs, each situated on two-layer or four-layer printed circuit boards under natural convection are modeled and compared in this study. One PBGA is also modeled and tested under 50, 100, and 225 lfpm to study heat exchange under forced convection. Three types of CSPs are also modeled under natural convection on a thermal test board without thermal enhancements. θ_JA values are calculated from the resultant simulation temperature profiles. The heat transfer coefficients are derived from the output of a user subroutine. A comparison is made with experimental data for similar package environments to validate the methodology, showing the model to predict junction temperatures within 10% of experimental measurements for the PBGAs and 13% for the smaller CSPs