Title :
Logic synthesis for programmable logic design
Author :
Ligthart, Michiel
Author_Institution :
Exemplar Logic Inc., Berkely, CA, USA
Abstract :
This paper presents a logic synthesis system for field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) based on either the Verilog HDL or VHDL. It describes aspects of synthesis and optimization specific to FPGAs and CPLDs, in contrast to CMOS gate-arrays. Particular attention is paid to architecture specific optimization, both on register transfer and logic level. The concept of the design methodology is proven by a real-world implementation of an actual design
Keywords :
circuit optimisation; field programmable gate arrays; hardware description languages; high level synthesis; programmable logic devices; CPLDs; FPGAs; VHDL; Verilog HDL; architecture specific optimization; complex programmable logic devices; design methodology; field programmable gate arrays; logic level; logic synthesis system; real-world implementation; register transfer level; CMOS logic circuits; Costs; Design methodology; Field programmable gate arrays; Hardware design languages; Logic arrays; Logic design; Logic devices; Programmable logic arrays; Programmable logic devices;
Conference_Titel :
WESCON/94. Idea/Microelectronics. Conference Record
Conference_Location :
Anaheim , CA
Print_ISBN :
0-7803-9992-7
DOI :
10.1109/WESCON.1994.403533
