Automating boundary scan design

Author

Olen, Mark ; Hofer, Dave

Author_Institution

DFT Technol. Group, Mentor Graphics Corp., Wilsonville, OR, USA

fYear

1994

fDate

27-29 Sep 1994

Firstpage

534

Lastpage

537

Abstract

ASIC and IC designers today are faced with the challenges of meeting strict design schedules and specifications, at the same time testability requirements are added. However, utilizing new top-down design techniques to automate the design, verification and testing of test logic such as IEEE 1149.1 boundary scan logic can be reduced from a six to eight week effort down to just days. This paper discusses a new technique of designing boundary scan in a top-down methodology, taking advantage of automated boundary-scan generation and automated logic synthesis

Keywords

application specific integrated circuits; boundary scan testing; circuit CAD; design for testability; integrated circuit design; integrated circuit testing; logic CAD; logic testing; ASIC design; CAD; IC design; IEEE 1149.1; automated boundary-scan generation; automated logic synthesis; boundary scan design; testing; top-down methodology; Application specific integrated circuits; Circuit testing; Design automation; Design methodology; Field programmable gate arrays; Graphics; Logic design; Logic devices; Logic testing; Product development;

fLanguage

English

Publisher

ieee

Conference_Titel

WESCON/94. Idea/Microelectronics. Conference Record

Conference_Location

Anaheim , CA

ISSN

1095-791X

Print_ISBN

0-7803-9992-7

Type

conf

DOI

10.1109/WESCON.1994.403542

Filename

403542