16×16 limited intermediate buffer switch module for ATM networks

Author

Gupta, Anil K. ; Barbosa, Luis Orozco ; Georganas, N.D.

Author_Institution

Dept. of Electr. Eng., Ottawa Univ., Ont., Canada

fYear

1991

fDate

2-5 Dec 1991

Firstpage

939

Abstract

An investigation is made of the performance of a nonblocking packet switch having input buffers and a limited amount of buffers within the switch fabric, where contention for the output ports occurs. This technique improves the performance significantly, while maintaining the switch fabric speed equal to that of the port speed. For uniform traffic, a 16×16 switch with head of line priority scheduling has an achievable throughput equal to 87.5%. The simulation results suggest that for unbalanced and bursty traffic, the performance of the switch does not degrade appreciably

Keywords

asynchronous transfer mode; electronic switching systems; packet switching; queueing theory; 16*16 limited intermediate buffer switch module; ATM networks; asynchronous transfer mode; bursty traffic; crossbar switch; head of line priority scheduling; nonblocking packet switch; performance; throughput; unbalanced traffic; uniform traffic; Asynchronous transfer mode; Central office; Communication system traffic control; Degradation; Error correction; Fabrics; ISDN; Protocols; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1991. GLOBECOM '91. 'Countdown to the New Millennium. Featuring a Mini-Theme on: Personal Communications Services

Conference_Location

Phoenix, AZ

Print_ISBN

0-87942-697-7

Type

conf

DOI

10.1109/GLOCOM.1991.188518

Filename

188518