The Sharp LH543620 1024×36 synchronous FIFO: a customer-defined product

The architecture for the new Sharp LH543620 1024×36 unidirectional synchronous FIFO was defined after extensive consultation with knowledgeable 36-bit-FIFO customers. It includes many customer-proposed new features, as well as capabilities which evolved from those of earlier FIFOs. It can perform many of the desired operations which ordinarily are done on full-wordwidth 36/32-bit data words in datapaths outside of processors. Thus, this FIFO often can eliminate needing gate arrays in datapaths, for performing these operations. The LH543620 is a fast 1024×36 synchronous unidirectional FIFO. It can connect to a 36-bit, 18-bit, or 9-bit data bus at either its input port or its output port. All flags may be made to operate synchronously, although asynchronous operation may be selected for the three middle flags if desired. 36-bit words may have the order of their bytes reversed as they pass through the FIFO; also, byte parity may be generated and checked for them. Two LH543620s may be operated tightly-coupled side-by-side, as a 72-bit-wide FIFO; or multiple LH543620s may be operated in a pipelined depth-cascaded configuration; or both of these types of operation may be implemented within the same application