DocumentCode :
2936020
Title :
Delta networks with multiple links and shared output buffers: a high performance architecture for packet switching
Author :
Ghosh, D. ; Daly, J.C.
Author_Institution :
Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA
fYear :
1991
fDate :
2-5 Dec 1991
Firstpage :
949
Abstract :
Analytical and simulation results are presented on the performance of delta networks constructed with crossbars having multiple channels per input/output (I/O) ports. The probability of internal blocking is reduced significantly when two or more parallel channels interconnect stages of crossbars. Using small buffers (about 20 packets) at the outputs of the networks a throughput exceeding 90% can be achieved by using 3 channels per port. With further increase in the number of channels and buffer size the throughput approaches 100%. These networks can be used in telecommunication switching employing asynchronous transfer mode and in multiprocessor systems
Keywords :
electronic switching systems; multiprocessor interconnection networks; packet switching; queueing theory; analysis; asynchronous transfer mode; crossbars; delta networks; high performance architecture; multiple links; multiprocessor systems; multistage interconnection networks; packet switching; shared output buffers; simulation; telecommunication switching; Analytical models; Bars; Buffer storage; Joining processes; Packet switching; Performance analysis; Sorting; Switches; Telecommunication switching; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Telecommunications Conference, 1991. GLOBECOM '91. 'Countdown to the New Millennium. Featuring a Mini-Theme on: Personal Communications Services
Conference_Location :
Phoenix, AZ
Print_ISBN :
0-87942-697-7
Type :
conf
DOI :
10.1109/GLOCOM.1991.188520
Filename :
188520
Link To Document :
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