Clock and sequence synchronization in diversity switching

In digital communication systems applying switching-type diversity, switching has to be hitless, i.e., no bits have to be omitted or repeated during the switchover process. This involves various synchronization tasks: the clock has to be synchronized so that no excess jitter occurs and the delay difference of the two sequences has to be aligned. The hang-up phenomenon is dealt with and a clock synchronizer design is described which is free of this problem and yields acceptable jitter only. The synchronization problem of random bit sequences is addressed, and performance parameters are analyzed