On the feasibility of a scalable opto-electronic CRCW shared memory

We discuss the results of a feasibility study of an opto-electronic shared memory with concurrent read, concurrent write capability. Unlike previous such work we consider a true hardware shared memory rather then a simulation on a tightly, optically connected distributed memory computer. We describe a design that could be implemented using compact integrated semiconductor modules and propose ways to solve two major problems faced by such a device: optical system complexity and parallel word level write consistency. It is shown that, in principle, a memory with GBytes capacity and a latency of less then 1 ns, accessed by up to 10⁵ processors could be feasible. Using devices currently available as laboratory prototypes and taking into account energy and crosstalk considerations a capacity of more then 1 MB and a latency of about 50 ns might be attained for up to 1000 processors