Low-latency skew-compensation circuits for parallel optical interconnections

We have developed a new skew-compensation method for parallel optical interconnections. To compensate for a skew of over one clock cycle, we have developed a new frame-coding technique called shuffled mBIC, which does not require a clock-rate conversion circuit; a new skew-measurement method, which is well suited for the addition of forward error correction; and a new bit-synchronization technique, which has a wide tolerance for the signal duty. Skew-compensation operation and error-correction adaptability with this method were confirmed using field-programmable gate arrays. Using this method, 12-ch skew-compensation LSIs using Si-Bipolar process for 1-Gbit/s/ch parallel optical interconnection were designed. These LSIs were designed with a maximum skew-compensation capacity of five clock cycles and a maximum latency of only nine clock cycles