Analysis of flip-chip packages using high resolution moire interferometry

Thermally induced stresses play an important role in controlling the structural reliability of flip-chip packages. As the demand for increased performance continues to shrink solder bump pitch and size, it becomes increasingly difficult to experimentally determine thermally induced displacements and strains within these packages. To address this issue, we have developed a high-resolution phase-shifting moire interferometry system to map thermally induced displacements and strains within underfilled flip-chip packages with a resolution up to 16 times greater than conventional moire interferometry. This technique has the capability to map displacement fields with 26 nm resolution, making it possible to accurately determine displacements and strains within features normally contained within one moire interference fringe. This system was demonstrated using a thermally loaded underfilled flip-chip package with 250 μm solder bump pitch. Displacement contour maps with 26 nm resolution were obtained to demonstrate the capability to measure thermal displacements within features as small as 30 μm. A second flip-chip package was analyzed to extract stress-intensity factors. A quantitative analysis was carried out at the die corner using experimental data and compared to finite element analysis results. A strain singularity analysis was also carried out. It was found that the experimental strains are higher and the strain singularity is lower than the finite element results