A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

Author

Herzel, Frank ; Glisic, Srdjan ; Osmany, Sabbir A. ; Scheytt, J. Christoph ; Schmalz, Klaus ; Winkler, Wolfgang ; Engels, Michael

Author_Institution

lHP, Frankfurt

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

82

Lastpage

85

Abstract

We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.

Keywords

BiCMOS integrated circuits; field effect MIMIC; frequency synthesizers; phase locked loops; transceivers; BiCMOS technology; SiGe; charge pump mismatch; constant loop bandwidth; dual-loop PLL architecture; frequency 48 GHz; frequency 60 GHz; loop bandwidth; low-noise PLL; low-noise frequency synthesizers; parallel charge pumps; size 0.25 micron; wireless transceiver; Bandwidth; Charge pumps; Communication system control; Frequency synthesizers; Phase locked loops; Phase noise; Resistors; Tuning; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical Meeting on

Conference_Location

Orlando, FL

Print_ISBN

978-1-4244-1855-8

Electronic_ISBN

978-1-4244-1856-5

Type

conf

DOI

10.1109/SMIC.2008.27

Filename

4446261