Title :
Design of a 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS
Author :
Yueyang, Chen ; Shun´an, Zhong ; Hua, Dang
Author_Institution :
Dept. of Electron. Eng., Beijing Inst. of Technol., Beijing
Abstract :
A 26 GHz Phase-Locked Frequency Synthesizer in 0.13 um CMOS process is designed. This frequency synthesizer generates quadrature outputs at 26 GHz. The PLL utilizing a QVCO with tuning range from 23.75 GHz to 28.25 GHz can be locked from 24 GHz to 28 GHz. The power consumption of the circuit is 34 mW with a power supply of 1.2 V. The phase noise of the QVCO is -95 dBc/Hz at 1 MHz offset and the Q-mismatch is 1.7deg. Circuits are simulated by Cadence Spectre in 0.13 mum Standard CMOS Process.
Keywords :
CMOS integrated circuits; frequency synthesizers; phase locked loops; voltage-controlled oscillators; CMOS process; Cadence Spectre; PLL; QVCO; frequency 23.75 GHz to 28.25 GHz; phase noise; phase-locked frequency synthesizer; power consumption; size 0.13 mum; voltage 1.2 V; CMOS process; Circuit optimization; Circuit simulation; Energy consumption; Frequency synthesizers; Phase locked loops; Phase noise; Power supplies; Process design; Tuning; CMOS; Phase-locked loop; frequency synthesizer; high-speed;
Conference_Titel :
Communications and Mobile Computing, 2009. CMC '09. WRI International Conference on
Conference_Location :
Yunnan
Print_ISBN :
978-0-7695-3501-2
DOI :
10.1109/CMC.2009.213
