Results of measurements on the APC3RH performance before and after irradiation

The “APC3RH” is a 16 channel CMOS analogue buffer chip designed to facilitate the readout of silicon diode based particle detectors. It is a radiation hard successor to the “APC3 chip”. Each channel consists of a fast pre-amplifier, integrator, 160 storage capacitors and a readout amplifier. The amplified current from the detector is integrated continuously, the resulting charge being stored every 25 ns on one of the capacitors. An on-chip control system selects another capacitor to store charge at the end of each integration period, avoiding those which are being read out or which contain charge destined to be read out. Charges are held on the capacitors until they are connected to the readout buffer or overwritten by new data, depending on the value of an external signal. The storage and reading cycles run concurrently. The on-chip buffer control circuitry ensures that data is read out in the chronological order of storage. The chip has been fabricated using a radiation hard technology capable of withstanding 10 Mrad. This paper describes its design and also the results of testing, the latter before and after irradiation. The purpose of the design was to evaluate the Harris AVLSIRA radiation hard process suitability for LHC applications. In this paper the performance of the design is compared with that of its non “rad hard” predecessor the APC3. Also the results of measurements made on the performance of the chip before and after irradiation are presented