A new parallel adaptive digital filter architecture for high speed digital subscriber line application

A new adaptive digital filter architecture for parallel output and update computations and its application to a high-speed digital subscriber line (HDSL) equalizer prototype are described. This architecture uses an output/update multiply-accumulate (MAC) pair to compute a finite impulse response (FIR) filter output in parallel with the updating of the filter taps via the leaky LMS algorithm. The MAC pair architecture provides a more efficient structure for adaptive filtering than would the use of its two processors in a normal serial LMS implementation. A second level of parallelism allows the use of multiple MAC pairs to implement long adaptive FIR filters. The viability of this architecture is demonstrated through experimental results obtained for a 800-kb/s HDSL equalizer research prototype