Title :
The design and simulation of a 400/533Mbps DDR-II SDRAM memory interconnect bus
Author :
Sharawi, Mohammad S. ; Al-Qdah, M.T.
Author_Institution :
Comput. Eng. Dept., Philadelphia Univ., Amman
Abstract :
A major bottleneck in todaypsilas computer system performance is the speed of the main memory bus. A memory bus should be carefully designed for good signal integrity (SI) and timing performance. This paper presents the design, modelling and simulation of a double data rate synchronous dynamic RAM (DDR-II SDRAM) memory bus operating at 400/533 Mbps. Three bus topologies are investigated and compared in terms of the amount of inter-symbol-interference (ISI) and the eye-width (EW). The topology with on-die-termination (ODT) gave about 95% improvement in ISI reduction, and about 37% and 12% improvement in the eye-width for the worst case write and read operations for the 400 Mbps data rate, respectively, when compared to the conventional mother board termination (MBT) scheme.
Keywords :
DRAM chips; integrated circuit design; integrated circuit modelling; system buses; DDR-II SDRAM; double data rate synchronous dynamic RAM memory bus; eyewidth; inter-symbol-interference; interconnect bus; mother board termination; on-die-termination; read operation; signal integrity; timing performance; write operation; Clocks; Computational modeling; DRAM chips; Design engineering; Integrated circuit interconnections; Random access memory; Registers; SDRAM; Signal design; Topology; DDR-II; Memory Bus; Signal Integrity; Stub Series Terminated Logic;
Conference_Titel :
Systems, Signals and Devices, 2008. IEEE SSD 2008. 5th International Multi-Conference on
Conference_Location :
Amman
Print_ISBN :
978-1-4244-2205-0
Electronic_ISBN :
978-1-4244-2206-7
DOI :
10.1109/SSD.2008.4632797
