Low Area Implementation of the Hash Function “Blue Midnight Wish 256” for FPGA Platforms

In cryptography and information security, hash functions are considered as the "Swiss army knife" - they are used in countless protocols and algorithms. In 2005, we witnessed a significant theoretical breakthrough in breaking the current cryptographic standard SHA-1. Although there is another family of standardized hash functions called SHA-2, ready to replace SHA-1 hash function, at the end of 2007, the National Institute of Standards and Technology (NIST) decided to start a 4 year world-wide development process, including a competition for the superior algorithm design, for choosing the next cryptographic hash standard SHA-3. Blue Midnight Wish is one of the proposed new designs in the SHA-3 competition that continues in the Second Round of the competition. In this paper, we describe the architecture and an FPGA implementation in several different Xilinx devices for the compression function of the Blue Midnight Wish hash function with a digest size of 256 bits(BMW-256). The main goal of this work is to implement the compression function of BMW-256 with as small as possible area.The proposed design synthesized for Xilinx FPGA Virtex "XCV300pq240" uses 2147 slices including the internal memory and just 1354 slices for the design that uses external memory. For comparison, SHA-256 Xilinx FPGA Virtex "XCV200pq240" design uses 4768 slices.