• DocumentCode
    2939750
  • Title

    A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter

  • Author

    Chang, Yu-Cheng ; Chiu, Wei-Hao ; Lin, Chen-Chien ; Lin, Tsung-Hsien

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2011
  • fDate
    14-16 Nov. 2011
  • Firstpage
    265
  • Lastpage
    268
  • Abstract
    A 3rd-order 1-bit continuous-time delta-sigma modulator (CTDSM) is reported. By shaping the 1-bit DAC feedback current with the proposed multi-step return-to-zero (RZ) waveform, the CTDSM achieves reduced sensitivity to clock jitter. In addition, the modulator adopts a proposed excess-loop-delay (ELD) compensation scheme. For a 4-MHz bandwidth, the CTDSM achieves a dynamic range of 71.5dB and a peak SNDR of 69 dB. Fabricated in a 0.18-μm CMOS, this chip dissipates 16.9 mW from a 1.8-V supply.
  • Keywords
    CMOS integrated circuits; delta-sigma modulation; 3rd-order continuous-time delta-sigma modulator; CMOS; DAC feedback current; bandwidth 4 MHz; clock jitter; excess-loop-delay compensation scheme; multistep return-to-zero waveform; noise figure 69 dB; power 16.9 mW; sensitivity reduction; size 0.18 mum; voltage 1.8 V; word length 1 bit; Clocks; Delay; Jitter; Modulation; Optical signal processing; Sensitivity; Shape;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4577-1784-0
  • Type

    conf

  • DOI
    10.1109/ASSCC.2011.6123561
  • Filename
    6123561
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2939750