A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture

Next-generation communication systems, such as 3GPP-LTE and WiMAX, have adopted turbo code as the channel coding technique. Turbo decoder usually requires many MAP decoders to achieve high-throughput requirement of the communication system, and thus the power consumption of turbo decoder becomes an important issue in the chip implementation. This paper proposes a new radix-16 modified log-MAP algorithm to enhance the throughput. The proposed algorithm includes a new modified term to calculate the logarithmic value of the sum of sixteen inputs efficiently, and thus to improve the detection performance. Finally, this study designs and implements a radix-16 modified log-MAP decoder using a 90nm 1P9M CMOS technology. The measurement results of the fabricated chip show that the proposed MAP decoder consumes only 3.32mW and achieves a maximum throughput 502Mbps. This chip with the power efficiency of 6.6 pJ/bit/iter outperforms the previously published MAP processors in the literature.